The main architectural differences
between Celerons, Pentium-IIs
and Pentium-IIIs can be found on our Intel
Stats pages. The performance differences between the Celeron-466 and
the PentiumIII-450 can be illustrated using our CPU
Comparator.
In summary, the main differences between Celerons and Pentiums are in
the areas of bus speed and L2 cache features. Both Pentium-II's and -III's
ship with 512kB of secondary (L2) CPU instruction cache. This allows the
CPU to store recently used instructions close by and is responsible for
much of their high performance.
The Celerons that Intel first introduced as a low-cost CPU alternative
(266 & 300MHz versions) were basically just Pentium-II's without any
L2 cache at all. This deficiency really punished Celeron performance when
compared to competitive AMD and Cyrix chips. In response, subsequent
Celeron versions (300A and up) were provided with 128kB of L2 cache.
Though only one-quarter the size of the Pentium cache, it was built to run
at the full speed of the respective CPU, rather than at half-speed as in
the Pentiums. Due to its higher manufacturing cost and technical issues,
the larger Pentium cache memory has always been set to run at only half
the speed of the CPU itself. For a full-speed L2 in a Pentium design, you
need to get into Intel's (much more expensive) Xeon
line.
What Intel plays down-- but nearly everyone knows-- is that the
full-speed, quarter-size Celeron cache gives them almost the same
performance as the half-speed, full-size cache gives Pentiums. Thus you'll
find that, for most applications, Celerons rated at the same MHz will
equal or better an equivalent Pentium-II, for a much lower price.
For example:
Celeron @ 466MHz x 128kB L2 @ 466MHz =>
Pentium-II @ 450MHz x 512kB L2 @ 225MHz
Pentium-III's are given an added boost with an inherently faster system
bus speed (100MHz vs. 66MHz for the Celerons) and Intel's new SSE 3D
instruction set. This combination of hardware and firmware enhancements
gives Pentium-III's a significant edge over the Celeron's smaller cache
and slower bus.
Additional discussion on L2 cache can be found here,
while more technical issues can be found at Intel's
developer web site.
