There are currently three flavours of L2
cache employed in today's CPUs. SRAM (Static RAM) cache generally
refers to the oldest of the three technologies, where the L2 cache is
located on the system motherboard running at the speed of the Front Side
Bus (FSB). An on-die L2 cache is a faster alternative to an SRAM cache,
particularly as CPU clock speeds continue to increase.
To illustrate the performance impacts of the different types of L2 cache,
take these CPUs as an example:
Intel's Celeron-A's demonstrate the newest implementation of L2 cache:
built onto the same die as the CPU itself. Check the Celeron
Stats page to see how the transistor count rises dramatically, as a
The Pentium-II uses a prior L2 technology, where the cache is built onto a
dedicated Back Side Bus (BSB), between the FSB and the CPU. Although the
BSB can run at the same speed as the CPU, cache memory capable of such
speeds is much more expensive. Therefore, in the Pentium-II, the more
economical half-speed cache is used (for a full-speed BSB, check out
Intel's Xeon line).
AMD's K6-2 illustrates the oldest, on-board L2 cache design. Though the
size of the cache is larger, its FSB speed limit shows its effect as CPU
clock speeds increase.
The original Celeron-300, bereft of L2 cache, shows a significant
performance penalty as a result. The L2-enabled Celeron-A at 300MHz is
able to at least keep pace with a Pentium-II or K6-2 at the same clock
At a processor speed of 400MHz, while its FSB runs at a pokey 66MHz, the
Celeron-A still remains in the same performance league as both the Pentium
II and the K6-2, mostly due to its newer on-die L2 cache.
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